A data transfer system is known in the art using a parallel interface, referred to as a Centronics parallel interface (hereafter abbreviated as Centronics interface). Between a host system and a peripheral, the peripheral unit, a data strobe signal (hereafter simply referred to as a strobe signal) is used to achieve synchronization of data output, and a busy signal sent from the peripheral unit to the host system indicates that the peripheral unit is engaged in a processing operation.
In this kind of data transfer system, the host system transmits the data to a data bus, and delivers the strobe signal when the busy signal is turned off. The peripheral unit receives the data on the data bus in synchronism with the rising edge of the strobe signal.
The interface requires a total of four accesses for each one byte transfer by the host system, including delivery of a data output to an input/output controller provided by the host system, a check of the busy signal, and delivery of a logical "0" and a logical "1" as the strobe signal.
Modification of this is a parallel interface synchronized with a change in data in which not only a change in the strobe signal, but also a change in the data to be transferred is utilized in the timing a data transfer, as disclosed, for example, in Japanese Laid-Open Patent Application No. 281,999/1995, where the host system determines from the busy signal whether or not a peripheral unit is engaged in a processing operation, and if not, transfers one byte of data and also inverts the strobe signal.
In response to the detection of an edge of the strobe signal, the peripheral unit generates a control signal to latch data transferred, and to transfer latched data to a memory by a DMA (direct memory access) process. In this instance, the host system does not effect a recognition of the busy signal until the transfer of a given number of data blocks is completed, and therefore as disclosed in the cited Application, a reduction in the time interval for data transfer is possible.
In a conventional data transfer system, there has been a problem that because the strobe signal is inverted each time the host system transfers one byte of data, it is necessary to provide a time interval for accessing the input/output controller mentioned above, thus retarding the data transfer rate by a corresponding amount.
There is another problem that since the transient responses of the data and the strobe signal, which are used in the parallel interface of the data change synchronized type, vary depending on the characteristics of the host system, the transceiver circuits used in the input and output of the peripheral unit and the quality of the cable which connects the host system and the peripheral unit, transition times of data signals and strobe signals vary from data transfer system to data transfer system, thus limiting the data transfer system to which such a scheme is applicable.